i would like to instantiate a vhdl DUT in sv testbench(used for uvm ),but it is impossible to connect them directly unless if i use other ways such binding, or signal spy if anyone here could possibly provide an example i will be so thankful.
In reply to Imane EL:
The interaction of VHDL and SystemVerilog is not covered in any language specification. Each tool handles this differently, so you will need to refer to your tool documentation or contact your tool vendor for additional assistance.