Instantiate a VHDL block that has a record as generic

SystemVerilog
1

Hello everyone.
I’m trying to instantiate a VHDL block that has 2 generics and one of them is a record type.

entity block_top is
   generic
   (
      constant ENABLE_g        : std_logic := '0';
      constant REGS_DEFAULT_g       : REGS_t := REGS_DEFAULT_c
   );
   port
   ( ...

type REGS_t is record
      ADDR                               : std_logic_vector(15 downto 00);
      LENGTH                             : std_logic_vector(15 downto 00);
...

I’ve tried importing the REGS_t to my TB module and created an object of that type and used this object as a parameter:


parameter bit[15:0] ADDR_p;
parameter bit[15:0] LENGTH_p;

regs_t generics;

initial
begin
generics.ADDR = ADDR_p;
generics.LENGTH = LENGTH_p;
end

\block.block_top #(
		.enable_g (3'b011),
                .regs_default_g (generics)
		)
		block_top
		( ...

But this gives me a error saying that that parameter needs to be constant. I also need to parameterize the fields of the record (ADDR, LENGTH) to implement testcases with different generics values. I’m avoiding making a wrapper to break that record and I’m wondering if there is another way to instantiate that generic. Thank you!

2

In reply to adenor:

There is no standard for mixing the VHDL and SystemVerilog standards, so you may need to consult your tools manual or support for examples.

But in SystemVerilog, you can only pass parameters to other parameters, so declare generics as a parameter instead of declaring as a variable.

parameter regs_t generics = '{ADDR:ADDR_p, LENGTH:LENGTH_p};
3

In reply to dave_59:

Hello Dave, thanks for your input. I’ve checked my tools manual and instantiating that generic of a record type is not supported. I’ve declared generics as a parameter and got this error: ** Error: (vsim-3051) VHDL generic ‘REGS_DEFAULT_g’ is the wrong type for the associated Verilog parameter. I’ll request for a RTL change to use a tool supported generic type.