Inout signal error in uvm interface

UVM
,
1

Hi all;

I written in interface
logic sda_out; //inout signal driving for bi-directional signal from UVC
wire sda; //inout signal driving for bi-directional signal from DUT
assign sda=sda_out;

I want verify master vip so i need assign some values to sda. once i assigned to sda questa simulator given error

** Error: (vsim-8220) tb/top.sv(33): This or another usage of ‘vif.sda’ inconsistent with ‘net’ object.

How handle inout signal?

2

Is
wire sda declared in interface definition alongwith
logic sda_out??

If yes then you should not use assign statement to assign a continuous changing values.

If sda and sda_out to be part of same interface, then declare sda also of logic type and use assign it in your top module.

example
interface master_vip_if();
logic sda_out;
logic sda;
…
endinterface

module top;

assign master_vip_if.sda = master_vip_if.sda_out;

Thanks,
Dipali

3

In reply to dipali:

Hi dipali…

I understand your solution thanks…
In my case their is no DUT or slave VIP, so i try to generating slave signal(data,ack) in top module, and slave signal(sda)to communicate with master.

4

So in that case you can directly connect sda in slave_if to sda_out in master_if in top module.

5

In reply to dipali:

Thanks for your quick response.

I done but sda signal is alone driving whatever its value,i thinking driving sda task/function with check certain conditions.

6

I think your requirement is not so clear from the description you have given.
Please elaborate in detail about the problem you are facing.

7

In reply to dipali:

I am new to UVM world, working on I2C vip. In I2C signal sda is bidirectional signal, for writing data on sda from my master driver for a particular address, i dont have slave vip or dut so i try generating red data in my master top module, for that i used vif.sda=0; but simulator given an error Error: (vsim-8220) tb/top.sv(33): This or another usage of ‘vif.sda’ inconsistent with ‘net’ object.
Please guide me how to do it?

8

It is better to develop slave class as well and connect these signals. Responding to an interface signals for a particular functionality from top module is not a good approach.

PS: The is not related to UVM!

9

In reply to dipali:

Thanks…i will do slave part also …

10

Modelsim/Questasim provides a ‘verror’ command to gain more insight for a specific error message. For this case, verror provides the following information:

Message # 8220:
The specified object name was used in a place where the type of that
object is not allowed. For example, using the hierarchical name of a
net as the LHS of a procedural assignment would produce this message.
NOTE 1: If more than one use of the object name exists, consider all
occurrences in resolving the error.
NOTE 2: If this error follows error number 8776 then please fix the
cause of 8776 before fixing this error.

The error is from your statement:

vif.sda=0;

Since sda is declared as a wire in your interface, you cannot assign a value with this procedural assignment. However, you can use:

vif.sda_out=0;

This will work since sda_out is of type ‘logic’.

11

Hi,

You can use here system verilog “alias” construct to connect bi-directional port of i2c master & slave.

Example

module top;

my_interface intf(clk);

// master i2c port
wire scl_m ;
wire sda_m ;
pullup p1(sda_m);
pullup p2(scl_m);
assign intf.i2c_m_scl_i = scl_m;
assign intf.i2c_m_sda_i = sda_m;
assign scl_m = intf.i2c_m_scl_en_o ? intf.i2c_m_scl_o : 1’bz;
assign sda_m = intf.i2c_m_sda_en_o ? intf.i2c_m_sda_o : 1’bz;

// slave i2c port
wire scl_s ;
wire sda_s ;
pullup p3(sda_s);
pullup p4(scl_s);
assign intf.SCL_In = scl_s;
assign intf.SDA_In = sda_s;
assign scl_s = intf.scl_en ? intf.SCL_Out : 1’bz ;
assign sda_s = intf.sda_en ? intf.SDA_Out : 1’bz ;

// connect master & slave bi-directional port.
alias scl_m = scl_s;
alias sda_m = sda_s;

endmodule