Inline static object initialization

SystemVerilog
, , , ,
3

In reply to cgales:

Is it possible to write component like below?

class some_component extends uvm_component;
  static some_item item_1;
  static some_item item_2;

  function void build_phase(uvm_phase phase);
    if(item_1==null) begin
      item_1=some_item::type_id::create("item_1");
      item_1.item_type=1;
    end
    if(item_2==null) begin
      item_2=some_item::type_id::create("item_2");
      item_2.item_type=2;
    end
  endfunction
endlass