How do I initialize a multidimensional associative array.
Eg:
string ARY[string][string];
ARY[“A”][“0”] = “abc”;
ARY[“A”][“1”] = “def”;
ARY[“B”][“0”] = “ghi”;
I tried doing like this
string ARY[string][string] = {“A”:“0”:“abc”,“A”:“1”:“def”,“B”:“0”:“ghi”};
But it is not compiling
If ordering your array elements this way does not make sense for your situation, then an assignment for each individual element might be the most readable.
How to assign or drive associative array elements?
My requirement is :
int arry[string];
wire penable_0, penable_1; //Assume drivers on these wires are present and their value will be either 0 or 1
arry[“a”] = penable_0;
arry[“b”] = penable_1;
SystemVerilog does not allow continuous assignments statements that include reference to dynamic elements, but you can get around this restriction by using a procedural block like
In continuation to the previous post, i tried using always @* arry[“a”] = penable_0;
My question this time is related to how assertions will sample this arry value.
penable_0 is driven on posedge clk in DUT.
I have an assertion module which is sampling arry[string] values and that too on same clk.
property xyz;
@(posedge clk)
arry[“a”] |-> (arry_1[“v”] == arry_1[“w”]); //arry_1 is driven the same way as arry[“a”]
endproperty
My understanding was, arry_1 values will be sampled in preponed region and DUT will drive penable_0 etc. on posedge clk which will happen in NBA region.
But i see that my assertion is picking the new value of arry_1[“v”] and [“w”].
I am using Cadence IES simulator.
If i change always @* to always @(posedge clk) arry[“a”] = penable_0;, it works ok.
Do you feel that it is expected? Or, there is something missing in my understanding.
For a multi dimensional associative array how can we use the inbuilt methods like exists(),delete().
what i mean to say is how to pass the index for a multidimensional associative array for inbuilt exists() method.
I found this thread from a google search.
I too am struggling, as the previous poster, on how to pass the index for a multidimensional associative array to the exists method.
E.g.
logic [31:0] noddy[int][int]; // associative array
//I've tried everything I can think of...
noddy.exists(4,6)
noddy.exists([4][6])
noddy.exists((4)(6)(8))
noddy.exists((4),(6))
noddy.exists([4],[6])
noddy.exists(4)(6)(8)
Think of arrays of arrays instead of multi-dimensional arrays. Most SystemVerilog methods that operate on unpacked arrays only deal with one dimension at a time. You can do
(noddy.exists(4) && noddy[4].exists(6))
And because SystemVerilog has expression short-circuiting, if the first term is false, the second term never evaluates. So that avoids an invalid reference.
Thank you very much Dave that worked a treat.
I see what you mean regarding thinking of array of arrays instead of multi-dimensional arrays.
Live and learn.
In reply to Witty:
Think of arrays of arrays instead of multi-dimensional arrays. Most SystemVerilog methods that operate on unpacked arrays only deal with one dimension at a time. You can do
(noddy.exists(4) && noddy[4].exists(6))
And because SystemVerilog has expression short-circuiting, if the first term is false, the second term never evaluates. So that avoids an invalid reference.
hello, dave, would please show us how to use delete() method? i can’t figure out it.