Indirect-address registers generate warning that they are not in address map (but dumping reg_map shows them)

UVM
,
1

In running the UVM 1.1d register model, I get the following warning for all 256 instances of
‘TABLES’.

however, TABLES appears when the reg-map is printed, and running the register-reset test causes them to be tested (per transcript).

What is causing this warning, and how do I fix it?

UVM_WARNING verilog_src/uvm-1.1d/src/reg/uvm_reg.svh(1749) @ 0: reporter [RegModel] Register ‘TABLES[0]’ is unmapped in map ‘reg_model.default_map’

2

In reply to erik.k.jessen@raytheon.com:

Could you please share some code? Especially your register model and how you are accessing these registers.

3

In reply to chr_sue:

I’m running the register example found in UVM 1.1d. I happen to be using Questasim, but since the warning is coming from within the UVM classes, I would presume that the warning occurs in all simulators.

4

In reply to chr_sue:

A slight side topic: the uvm_reg_indirect_data.configure() expects a vector of uvm_reg.
The documentation implies that vector[N] is accessed when the indirect-address register has a value of N. I.e. there’s no way to implement a sparsely-populated indirect-address map, where there might be registers at (for example) addresses 0, 2, and 3. But no register at address 1. Have I missed anything?

5

In reply to erik.k.jessen@raytheon.com:

I had a deeper look to the example. First, the warning is true, because the indirect registers are not in the register map. Second, the warning Comes out of the command model.print().
If you replace this line with something other the warning disappears.
Because tzhe model.print is quite unspecific I do not use it.
Better Information about your registers are provided by doing something like this:

function void start_of_simulation_phase(uvm_phase phase);
   uvm_reg       regs[$];
   string name;
   model.default_map.get_registers(regs);
   `uvm_info(get_type_name(), $psprintf("found %d registers", regs.size()), UVM_MEDIUM)
   for (int j = 0; j < regs.size(); j++) 
     `uvm_info(get_type_name(), $psprintf("reg[%0d]: %s", j, regs[j].get_name()), UVM_HIGH)
endfunction : start_of_simulation_phase