Increment operator does not increment a ref variable in the first iteration

SystemVerilog
,
1 
class func_const_ref;
int aa;

task checkref( ref int bbb, ref int bb);
  for(int ii=0; ii<5; ii++) begin
	bb = bb++;
	$display(bb);
	$display(bb++);
	bbb++;
	$display(bbb);
  end
endtask
endclass

module top();
int a=10, bbbb=0;
initial begin
	func_const_ref fcrt;
	fcrt = new();
	fcrt.checkref(bbbb, a);
	$display(bbbb);
end

endmodule

Result:
10
10
1
11
11
2
12
12
3
13
13
4
14
14
5
5

I was expecting to see the first “$display(bb++);” to display 11 instead of 10.

Question:
Why does $display(bb++) shows the incremented value is the same as the argument passed the first time when for loop is entered.

2

In reply to natasv:

This has nothing to do with function/task arguments and just poor coding. The evaluation of the expression

bb = bb++;

is indeterminate.

The ordering of assignment operations relative to any other operation within an expression is undefined.

That means the value of bb++ is 10 in the RHS of the assignment, but whether the variable bb gets updated with the incremented value before the blocking assignment is undefined.