According to VA in the register/abstraction section, the reset method only resets the mirror value and does not perform a bus cycle. Then in the table at the bottom of the page, it says reset works front-door, which I thought meant a physical bus cycle. Which is it?
Thanks for your bug report, I agree. This aspect of the table is quite confusing and I will revise it… possibly by adding a third set of columns for ‘internal’ for those APIs (not just reset() - there are others) which affect only the internal model and do not update either front-door or back-door accesses. The intent of the table was to show where the different APIs could be applied: at field or reg or block level.
Note: although reset() does not affect the DUT, a subsequent call to update() (with either UVM_FRONTDOOR or UVM_BACKDOOR access specified) would then propagate the reset() outcome to the DUT.
In reply to gordon:
What I am looking for the a proper method to model a write-only register which will always read back 0. I want an access method that will perform a write (of a ‘1’), but leave the mirror value as 0, because that is how the RTL is coded. I want to be able to write a bit to ‘1’, have the write bus cycle occur (so a set/update), then be able to turn around and do that again. Currently, I need to manually change the mirror (which is what I was trying to do with reset, which seemed to work) in between my writes. Otherwise the first write sets the mirror to ‘1’ and the second write is ignored because it already thinks the mirror (and thus the register bit) is ‘1’, so it performs no bus cycle. None of the default register field access methods will do what I want. The only ways I had found to get around this were:
a. always do this operation with a write (which sort of defeats the purpose of being able to abstract out the individual register bits
b. do my set/update, then do a dummy read to update the mirror (will read back 0), then do my set/update. Fine, except I am having to do the extra physical read in between.
c. do the reset in between, which seemed to work and did not cause an extra physical read bus cycle