Including Files From Command line

SystemVerilog
,
1

Hello,
Kindly help me with the following trouble.

i am having

file1:TOP.sv

module Top();
…
…
Test();
…
endmodule

File2 : Testcase1.sv

module Test();
…
endmodule

File3: Testcase2.sv

module Test();
…
endmodule

I want to include either File2.sv or File3.sv in File1.sv from command line. I searched something related to $plusargs but i am not getting hoe to use it.

2

In reply to Mangalji:

Please elaborate your problem. It looks like you need a simple shell script to choose between two options, correct?

3

Shell script would look like this:

#! /bin/csh -f

if($#argv) then
  set var = $1
  <run file2>
else
  <default run command>
endif

On the command line:

>> source <script_name> <filename>
4

In reply to Sushrut Veerapur:

I want to compile Top.sv only but What should i use to include File1.sv or File2.sv in Top.sv from command line. at a time i want to include only one of them.

5

In reply to Mangalji:

On what basis do you want to choose testcase1 or testcase2?

6

In reply to dave_59:

file1.sv contains some scenario which generates testcase and File2.sv contains another scenario that generates another testcase. I want to run testcase1 and then testcase2 but both the testcases are in different file. i want to choose wither of them from command line.

or simply consider the feature +uvm_testname.

7

In reply to Mangalji:

I have not tried any of below methods.

I think you can use ifdef like below

File test1.v
`ifdef TEST1

module Test();

endmodule
`endif

File test2.v

`ifdef TEST2
module Test();

endmodule
`endif

when compiling the RTL list pass the required define in the command line for example for MTI.

vlog +define+TEST1 -f filelist

or another method
Remove all the Test Files from filelist and Pass file name at command line
vlog test1.v -f filelist