Hi All,
In RTL simulation, the backdoor path of registers can be filled with the “HDL_PATH” character segment in CSV, XML and other files according to the RTL specification rules, and the register model accessed using the built-in backdoor of UVM can be generated through scripts or tools. However, in SDF nettable simulation, the paths of some registers change greatly. It is not a simple concatenation of the RTL path “.q”, so I would like to ask you how to deal with the register backdoor access in SDF netlist simulation? At present, I can think of the following solutions:
1, In seq, use uvm_hdl_force/deposit and uvm_hdl_read instead of register operation;
2, USE TCL script proc, package the force and read operation of register signals in the netlist;
3, Use user-define backdoor access, use macro to distinguish RTL simulation from netlist simulation, and define the register backdoor path of RTL simulation and netlist simulation. The backdoor path of RTL simulation can be generated using CSV, XML and other files in the early stage, while the register backdoor path of netlist simulation needs to be filled in manually;
So I would like to ask you how to deal with the register backdoor access in netlist simulation? Could you provide a user-define register backdoor access example, thank you very much!