In reply to peter:
It would really help other if you said more than just “It does not work”. If your top level module was written in Verilog, you would get a syntax error because it would not recognize the program block syntax.
Your main problems as Prashant showed you are that your were missing an initial block, and you need to instantiate your nested program block. But the example is more complicated than it needs to be.
module top();
test1 t();
task test();
$display("I am in outside \n");
endtask
program test1();
initial test();
endprogram : test1
endmodule
In Verilog/SystemVerilog, a task/function call will search up the hierarchy to find that task/function if it is not defined locally. This works regardless of module/program/interface, or if the module/program/Interface definition is nested or not.
BYW I strongly discourage the use of program blocks.