In-line random variable Control

SystemVerilog
,
1

Hi ,

I have the Following snippets ::



SNIPPET 1
rand byte x, y;
byte v, w;
constraint c1 { x < v && y > w ; ) // Logical AND





SNIPPET 2

rand byte x, y;
byte v, w;
constraint c1 { x < v ; y > w ; ) // Separated by semicolon

[Q1] Is there any difference between the 2 Snippets ?

I use it in the following Code



class CA;

rand logic x , y; // Using 4 State Type with Default 'X'

byte v, w; // 2 State type Defaults to 0

constraint c1 { x < v ; y > w ; }

endclass

CA c1;


initial begin

c1 = new();

c1.x = 0;
c1.y = 0;
// Made 0 explicitly so that Constraints Don't Fail
if ( c1.randomize(v,w) )
  $display("Failure");  

$display("%p",c1);  // I get OUTPUT :: '{x:0, y:0, v:0, w:0} , Why so ??

repeat(5)
begin
  
if (  c1.randomize(v,w) )
   $display("%p",c1);  
else
  $display("Failure"); // Get Failure Always 
end

  
end

In the First Display I get that randomization fails , but not sure why ? .

w Being 2 State Signed can take values Less than 0 . Even v can take values up to +127

Regards,
AGIS

2

In reply to Etrx91:

A1. There is no differences. All active constraints are effectively ANDed together.
A2. Quoting the LRM “When one or both operands of a relational expression are unsigned, the expression shall be interpreted as a comparison between unsigned values.”