Import package based on define

SystemVerilog
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2

In reply to Guy Levenb:

There is no `ifeq in SystemVerilog; the complexity of its datatypes makes it difficult to evaluate in a preprocessor.

Why not use

`define  PACKAGE_TO_USE package_1

import `PACKAGE_TO_USE::*;

Note that most tools allow you to put different versions of the same package into different libraries, and then you can choose which library to use when compile the code that imports it.