Hi Forum,
I wanted to model a RC register for my Tb, however I am confused on the following ::
(1) If user tries to read the register,
(a) Would they observe Rdata as zero [ or ]
(b) The prior value which RTL has written to it.RTL clears it on same clock such that a 2nd read to the RC register would result in zero value being read by user.
(2) When should the RTL clear the register ? i.e is it done on the same clock that user tries to read it.
My existing code looks like this
module traffic ( input pclk,
input presetn,
input [31:0] paddr,
input [31:0] pwdata,
input psel,
input pwrite,
input penable,
// Outputs
output [31:0] prdata);
reg [31:0] state_reg; // Lower 10-bits are "RC" register mapped to Addr:'hC. Upper bits are reserved
// other register definition
// Set all registers to default values
always @ (posedge pclk or negedge preset_n) begin
if (!preset_n) begin
state_reg <= 0;
.....
end
else begin
state_reg <= ( (paddr=='hC) & psel & penable & !pwrite ) ? 0 : ($urandom % 1024); // Can't be written by FW. RTL writes based on internal logic
// Additional Sequential writes
end
end
// Provide read data
always_comb begin
if (psel & !pwrite & penable)
case (paddr)
............
'hc : rdata_tmp = { 22'b0 , 10'b0 }; // "RC" field in state_reg[9:0];
endcase
end
assign prdata = (psel & penable & !pwrite) ? rdata_tmp : 'hz;
endmodule
Any suggestions are welcome.
Thanks in Advance,
Arshi