Illegal range in part select

SystemVerilog
2

In reply to zz8318:

I don’t think we can use variables in both [msb:lsb] for range select , but plz see if below solution might help

task my_check(bit [19:0] addr, bit [31:0] expect_data, int shift, int width);
    bit [31:0] my_data;
    bit [31:0] local_my_data;
    int msb = shift+width-1;
    int lsb = shift;
    for(int i=0; i < width; i++) local_my_data[i] = 1'b1;
    my_env.my_ral_mdl.read(status, value, UVM_BACKDOOR);       // use ral backdoor method to read register
    my_data = (value >> lsb) & local_my_data;
    ......
endtask