Illegal Format specifier Error

SystemVerilog
1

Can some body tell me what is wrong in this display statement?

module test;
class a;

rand int d[10];
rand int b;
rand int index_max;

constraint c {
foreach (d[i]) d[i] inside {[1:99]};
index_max inside {[1:10]};
b == d.sum(item) with (item.index <= index_max ? item : 0);   

}
endclass
initial begin
a A = new();

$display ("The value of a is %d, index_max is %d, B is %d",A.d,A.index_max,A.b);

end
endmodule

Here is the Error :
Error-[IFSF] Illegal format specifier
./chaining.sv, 19
“$display(“The value of a is %d, index_max is %d, B is %d”, A.d, A.index_max, A.b);”
‘d’ is not a valid format specification for argument A.d
Please correct the error and recompile.

2

In reply to rag123:

Not sure what you are expecting to print, but the variable d is an unpacked array. So you either need to use ‘%0p’ to print it out as an assignment pattern, or select an element of d.

3

In reply to dave_59:

Thanks Dave