Ifndef construct

SystemVerilog
, ,
1

I have started looking into SV and came across construct a lot.

ifndef TEXT_IDENTIFIER define TEXT_IDENTIFIER
//blah blah blah code here

`endif

Code blah blah blah code gets executed even if TEXT_IDENTIFIER was defined just below it.

  1. So in looking at compiler directive, does compiler read line by line and 2nd line define TEXT_IDENTIFIER is not read when ifndef was encountered and thus blah blah blah code gets executed?

  2. If answer to 1 is yes, then why do we write code like this? I have seen similar code in uvm_pkg.sv

2

In reply to aashishs2603:

  1. Yes, the compiler reads text line-by-line, or more succinctly character-by-character.
  2. This style of compile guards is mostly unnecessary in SystemVerilog. See system verilog - Include guards in SystemVerilog - Stack Overflow
3

In reply to dave_59:

Thanks Dave,

Stack overflow link you pointed is extremely helpful.

Thanks
Aashish