Ifdef empty list in case statement

SystemVerilog
,
1

Suppose I had some code like below:

`ifndef MY_LIST
`define MY_LIST 'd0, 'd1, 'd2, 'd3
`endif

always_comb begin
   foo = 1'b0;
   if (some_condition) begin
      case (some_input)
         `MY_LIST,
         `SOME_OTHER_LIST: foo = 1'b1;
         default: foo = 'b0;
      endcase
   end
endfunction

MY_LIST is actually an autogenerated list by a script. It’s possible this list could be empty. If so, I’d be left with:

`ifndef MY_LIST
`define MY_LIST
`endif

This unfortunately causes a compile syntax error. I noticed that if I guard the usage like below, the compile succeeds.


      case (some_input)
`ifdef SOME_FLAG_THAT_IS_NOT_DEFINED
         `MY_LIST,
`endif
         `SOME_OTHER_LIST: foo = 1'b1;
         default: foo = 'b0;
      endcase

This would require me to know ahead of time that the list is empty and create some sort of special `define to indicate this particular list is empty. I’d also have to have these guards all over the place for every list that is potentially empty.

Is there a more elegant way to solve this problem? I don’t have to use an `ifdef list if that helps.

2

In reply to atashinchi:

Use the case inside statement, then you can declare your lists as arrays, perhaps in a package, that gets imported.

module top;
  parameter int MY_LIST1[] =  '{'d0, 'd1, 'd2, 'd3};
  parameter int MY_LIST2[] =  '{};
  parameter int MY_LIST3[] =  '{'d0, 'd5, 'd2, 'd3};
  
  bit foo,some_condition;
  int some_input;
   initial begin
     some_input=5;
     case (some_input) inside
         MY_LIST1,
         MY_LIST2,
         MY_LIST3: foo = 1'b1;
         default: foo = 'b0;
      endcase
     $display(foo);
   end
endmodule