Ifdef at the beginning of the file

SystemVerilog
1

I am wondering why would one write something like this at the beginning of every class definition file:

ifndef APB_AGENT__SV define APB_AGENT__SV

Is it to avoid a class being included multiple times? If so, what is the recommended naming convention?

Thanks.

2

Yes, it is to prevent a file that has been
`included multiple times from being compiled multiple times. People use this methodology so they don’t have to spend as much effort figuring out all the file order dependencies. Note that the compiler still has to read the file and parse it enough to find the matching
`endif

The uppercase name of the file is the typical naming convention, with illegal identifier characters converted to _(underscore). If the file name is not unique, the directory name should get prefixed as well.

3

In reply to dave_59:

Great, that is very helpful. Thanks