If i not put semicolon in my code , It;s running. How it's?

SystemVerilog
,
1

Hi All,
This is code;

   module top;
               int a;
               bit b;
               initial  begin
                  a=5;
                  b=1;
                  #a                 --> Here i am not put semicolon
                  b=0;
                  #a;
                end
           endmodule

          I am not put semicolon in my code.
          but it's running compilation free.
          How it's?

Thanks
Raja

2

In reply to Rajaraman Rak7:

See wait construct | Verification Academy