If-else VS implication Constraint

SystemVerilog
,
1

Hi all ,

Is there a difference between if-else and implication Constraint ?


rand bit [1:0] a , b ;

constraint {    if ( a == 1 ) 
                 b == 3 ; 
            }

The Same could be written through Implication Constraint as well


rand bit [1:0] a , b ;

constraint {     
               ( a == 1 ) -> ( b == 3 ) ; 
            }

We could even club multiple expression when a == 1 is True


rand bit [1:0] a , b , c ;

constraint {    if ( a == 1 ) 
               {  b == 3 ; c == 3 ; } 
            }



rand bit [1:0] a , b , c ;

constraint {   ( a == 1 ) -> ( b == 3 ; c == 3 ; )
           }

So can they used interchangeably or is there any scenario where one is preferred over other ?

2

In reply to TC_2017:

Quoting from the LRM

The if–else style constraint declarations are equivalent to implications.

3

In reply to logie:

Personally I would recommend the implication syntax… People tend to
read the if-then-else constraint like a procedural-if statement.