I wanted to make a component more reusable. I wanted to select various types of memories based on the class parameters. This is what I have now:
class qvip_memory_agent_ext #(string MEM_T = "mgc_ddr", type CONFIG_T, type TRANS_T) extends uvm_component;
I wanted to select which mem type in the build phase by the following:
function void build_phase(uvm_phase phase);
super.build_phase(phase);
monitored_transaction = TRANS_T ::type_id::create("monitored_transaction");
monitored_transaction.m_receive_id = get_stream_id (this);
vip_config_h = CONFIG_T::type_id::create("vip_config_h");
if (MEM_T == "mgc_pnor") begin
if( !uvm_config_db #( virtual mgc_pnor )::get( null , "UVMF_VIRTUAL_INTERFACES" , if_name , vip_config_h.m_bfm ) ) begin
$stacktrace;
`uvm_fatal("CFG" , $sformatf("uvm_config_db #( virtual mvc_pnor )::get cannot find interface bfm resource with interface_name %s",if_name ))
end
end else begin
if( !uvm_config_db #( virtual mgc_ddr )::get( null , "UVMF_VIRTUAL_INTERFACES" , if_name , vip_config_h.m_bfm ) ) begin
$stacktrace;
`uvm_fatal("CFG" , $sformatf("uvm_config_db #( virtual mvc_ddr )::get cannot find interface bfm resource with interface_name %s",if_name ))
end
end
endfunction
My environment makes a typedef of the component:
typedef qvip_memory_agent_ext #(.MEM_T("mgc_pnor"),.TRANS_T(pnor_host_write),.CONFIG_T(pnor_vip_config)) my_flash_t;
my_flash_t my_flash;
This compiles but the sim load complains:
** Error: (vsim-13216) Illegal assignment to type ‘virtual mgc_ddr’ from type ‘virtual mgc_pnor’:
…
The line number given in the sim load error refers to the uvm_config_db get in the else statement. I didn’t think the ‘else’ would get hit during the load. Can anyone advise a better way of doing this? thx