If condition for Replaceable `define

SystemVerilog
,
1

Hello all,

We have one macro defined e.g. `define MAX_NUMBER_OF_LANES 4. Now from command line we change its value to 2. And we have used this macro for defining the array of interface.

xyz_interface tx_if[(`MAX_NUMBER_OF_LANES-1) : 0];

Now we access interface using index as per following function. This function is getting called from configuration class.

  function virtual tx_if get_if(int idx);
   case (idx)
      0 : get_if = tx_if[0];
      1 : get_if = tx_if[1];
      2 : get_if = tx_if[2];
      3 : get_if = tx_if[3];
      default:begin
        $display("Lane index %0d not supported.", idx);
      end
    endcase
  endfunction

When we have number of interface =4 the above function works fine. But when we provide the macro MAX_NUMBER_OF_LANES to 2 from command line then it gives compilation error from above function because size of tx_if is only 2.

How can we modified above function by just adding some stuff like checking the value of define in case statement and then compile that piece of code?

Thanks in advance…

2

You can create an static array of virtual interface variables to replace the function

xyz_interface tx_if[(`MAX_NUMBER_OF_LANES-1) : 0];
virtual xyz_interface get_if[(`MAX_NUMBER_OF_LANES-1) : 0];
for(genvar i;i<`MAX_NUMBER_OF_LANES;i++) begin
  initial get_if[i] = tx_if[i];
end