If a certain function parameter is passed by 'ref' how to make following parameters to be non-ref?

SystemVerilog
1

In SystemVerilog value can be passed via reference, which is indicated by ref keyword. But if a function has other parameters declared after the ref parameter they also seem to behave like passed-by-reference. Why it is so? (or what rule in LRM applies to that?)

My first thought to this counter-intuitive behavior was ‘it’s simulator bug’, so I checked other tools on edaplayground.com. The results were consistent, so it’s certainly intended behavior. In this case how to undo the ref if I really want to preserve the parameter order I like?

Code listing:


class Test;
  function genArray(int count, ref byte arr[]);
    arr = new[count];
    for(int i=0; i<count; i++)
      arr[i] = $urandom();
  endfunction
  
  function genArrayWrong(ref byte arr[], int count);
    // ??
    genArray(count, arr);
  endfunction
endclass

module tb;
  
  Test t;
  byte randomStuff[];
  
  initial begin
    int myCount = 14;
    t = new;
    t.genArray(14, randomStuff);           // ok
    t.genArrayWrong(randomStuff, myCount); // ok
    //t.genArrayWrong(randomStuff, 14);    // won't compile
    
    $display("random array: %p", randomStuff);
    $finish;
  end
  
endmodule
2

In reply to mmaciag:

The implicit direction of the first argument is input. The implicit direction of the successive arguments take on the direction of the preceding argument. Directions are: input, output, inout, and ref.

1 Like
3

In reply to dave_59:

Thanks for quick answer. That’s it! I didn’t know that ref is just another kind of ‘direction’.

The code below compiles fine:


function genArrayWrong(ref byte arr[], input int count);
    genArray(count, arr);
endfunction
1 Like