Iam getting vlog-2730 error in compilation

SystemVerilog
,
1

Hi

Iam getting compilation error when i use soft constraint in below version of QuestaSim vlog 10.1a.

My code as below
:

constraint data_size_c
{
soft data.size inside {[0 : 8196]};
}

Error iam getting is:

  • Error: /users/bharath.musku/SATA_4Apr/sata-vip/Source_Code/ei_sata_vip/sv/ei_sata_tl/inc/ei_sata_tl_packet.svh(185): (vlog-2730) Undefined variable: ‘soft’.
2

SystemVerilog added soft constraints in the 2012 version of the standard. This forum is not for tool specific help, but I suggest you get a newer version of Questa that supports it.

3

I think Questa 10.2 and above support this feature (with -sv12compat switch for vlog command)

4

In reply to milner:

Hello Milner/Dave,

Yes i used questa 10.2c version and this new feauture worked.

Thanks
Bharath