In reply to chr_sue:
I2C i am trying for my own understanding of writing UVM testbench for bus protocols
this SCL is generated by master it remains in high state till the START sequence is detected
once START is detected the scl will go low
next the 7 or 10 bit address are driven by master bit by bit whenever SCL is low and sampled by slave when SCL is high
so how to generate this SCL clock signal from the master driver (consider single master and single slave configuration )
i am asking logic