I need small help in writing constraint

SystemVerilog
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1

I am struct at in my ahb3lite project. I want to write a constraint randomization for example :
take INCR 4:
in one clock cycle I need to send NONSEQ and remaining 3 clock cycles I need to send SEQ

2

In reply to marathuteja:

You can build a state machine using non-random variables and post_randomize(). Here’s a quick example, untested:

typedef enum bit [2:0] {SINGLE,INCR,INCR4,...} hburst_e;
typedef enum bit [1:0] {IDLE,BUSY,NONSEQ,SEQ } htrans_e;
class ahb3trans;
 rand hburst_e HBURST;
 rand htrans_e HTRANS;
 int count;
 constraint seq_c { if (count > 0) HTRANS == SEQ;
                    if (count==0 && HBURST != SINGLE) HTRANS == SEQ;
}

function void post_randomize();
  if (HBURST==INCR4 && count = 0) count = 3;
     else if (count > 0) count--;
endfunction
endclass
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