I’m not able to read a hdl path using uvm_hdl_read

UVM
1

Trying to read a hdl path using uvm_hdl_read inside my UVM tetsbecnch. The exixts since I have already confirmed using uvm_check_path. Somebody pleas help

2

In reply to kevin488:

Do you get an error message or what is your problem in some more detail?

3

In reply to chr_sue:

I have given
If(!uvm_hdl_read(“chipset_tb_top.ser.mode_strap”,strap))
‘UVM_error()

It is giving me this error: unable to locate hdl path , either the names is incorrect or you may not have PLI/ACC visibility

4

In reply to kevin488:

Check your tool’s user manual for UVM backdoor accessibility.

5

In reply to dave_59:

I have used the same statement inside build phase to see if it works and it is working but when I use in a function it throws up the uvm error. By the way I’m using simvision

6

In reply to kevin488:

This Mentor/Siemens EDA sponsored public forum is not for discussing tool specific usage or issues. Please read your tool’s user manual or contact your tool vendor directly for support.