properties and sequences can have formal arguments that can be untyped. You can’t use the bind because the binding module would have parameters that would need to be sized in the binding. However, you can use the include of a file where the properties use untyped formal arguments. BTW, with the include, you don’t need to have the properties with arguments, Below is an example.
// file props.sv
property p_go2(datain,
dataout);
go |=> datain==dataout+1'b1;
endproperty;
ap_go_with_include: assert property(@(posedge clk) p_go2(data_in, data_out));
//file sync_ff
module sync_dff#(parameter [31:0] SIZE = 32'd1)
(input bit clk,rstn, go,
input logic[SIZE-1:0] data_in,
output logic[SIZE-1:0] data_out);
`include "props.sv"
// property with typed formal arguments
property p_go(logic[SIZE-1:0] datain,
logic[SIZE-1:0] dataout);
go |=> datain==dataout+1'b1;
endproperty;
ap_go: assert property(@(posedge clk) p_go(data_in, data_out));
// ...
endmodule
// This module is being used in many locations.
// Some with SIZE = 1, some with SIZE = 2, and some with SIZE = 8...etc.
// Is it possible to create a generic property for this module with different SIZE definition?
// If possible, what is the easiest way to bind without binding instance individual according to the SIZE?
Ben Cohen Training for VMM, SVA (831) 345-1759
http://www.systemverilog.us/ ben@systemverilog.us
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115