In reply to chr_sue:
In reply to Arun_Rajha:
It looks like your BFM is considered as a behavioral model of your DUT. If it has the same port connections as your RTL DUT will have you can instantiate this module in the toplevel of your testbench.
But note, even if the DUT does not exist, but you have all the functional intefaces/ports defiend you can develop and debug your UVM testbench.
yes i can debug with the help of interface or ports but my doubt here is does the bfm will mimic the working of entire memory(DUT which is not here in my case). If it mimics then how does it differs from the real memory(DUT).