In reply to Arun_Rajha:
It looks like your BFM is considered as a behavioral model of your DUT. If it has the same port connections as your RTL DUT will have you can instantiate this module in the toplevel of your testbench.
But note, even if the DUT does not exist, but you have all the functional intefaces/ports defiend you can develop and debug your UVM testbench.