How we can write coverage on Immediate assertions

SystemVerilog
1

Do we have any direct syntax which help us to write coverage on Immediate assertions

As “cover property”, we can write coverage on CONCURRENT ASSERTIONS.

Thanks in advance

2

You’ll have to use the covergoup and activate the sample.
Of course, you can always use the cover property of the expression, but then, you’ll need a clocking event.
Ben Cohen ben@systemverilog.us

3

By default in Questa, all attempted immediate assertions are automatically included in the coverage analysis.

4

SVA allows immediate cover just like concurrent cover. BTW you seem to be mixing terms on “property” vs. “assertion”

You said:

As “cover property”, we can write coverage on CONCURRENT ASSERTIONS.

Rather it is better stated as:

As “cover property”, we can write coverage on CONCURRENT PROPERTIES.

HTH
Ajeetha, CVC