module asser #(ADDR_BITS = 32, DATA_BITS = 32, TXID_BITS = 4, STRB_BITS = DATA_BITS / 8)
( input logic aclk,areset_n,
// write address channel signals
input [TXID_BITS - 1:0] awid,
input [ADDR_BITS - 1:0] awaddr,
input [ 3:0] awlen,
input [ 2:0] awsize,
input logic[1:0] awburst,
input logic[1:0] awlock,
input logic[3:0] awcache,
input logic[2:0] awprot,
input awvalid,
input awready,
// write data channel signals
input [TXID_BITS - 1:0] wid,
input [DATA_BITS - 1:0] wdata,
input [STRB_BITS - 1:0] wstrb,
input wlast,
input wvalid,
input wready,
// write response channel signals
input [TXID_BITS - 1:0] bid,
input logic[1:0] bresp,
input bvalid,
input bready);
// int que[$];
int awid_arry[int];
// int temp,temp2;
int b;
always @(posedge aclk)
begin
if( awvalid==1 && awready==1 )
begin
awid_arry[awid] = awlen + 1;
end
end
always @(posedge aclk)
begin
if( wvalid==1 && wready==1 )
begin
if(awid_arry.exists(wid))
begin
if( awid_arry[wid]>0 )begin
awid_arry[wid]–;
b = awid_arry[wid];
$display(“vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv”);end
else begin
$error(“id is not valid”);end
end
end
else begin
$error( “not exist”);end
end
sequence s1;
int cnt[int];
@( posedge aclk)
(awvalid && awready ) ##0 (awid_arry[awid] = awlen) ##0 (cnt[awid]++,wvalid)[*0:$] ##0 ( cnt[awid] == awid_arry[awid] );
endsequence
property p1;
##0 s1;
endproperty
ERRRRRRRRRRRRRRRRRRRRRR: assert property(p1);
endmodule
is it week assertion?
plz tell me how we can write assertion for axi master slave
in my code master vip master send awaddr and control information such as awlen per posedge aclk where slave vip received it .same as master send write data and slave received it bt i want to assert on such as if master send awlen=7 after that master send data transfer 8 times then my assertion will shout erro…
and what is the mistake in my sequence block?