How we can replace value to the field in add sequnce of uvm

UVM
,
1

HI,

I am using UVM add_sequence to generate random sequence :

class rand_sequence_valid extends uvm_sequence_library#(sequence_item);
rand bit [15:0] address;

function new(string name=“rand_sequence_valid”);
add_sequence(seq_1::get_type());
add_sequence(seq_2:get_type());
add_sequence(seq_3::get_type());
add_sequence(seq_4::get_type());
init_sequence_library();
endfunction
endclass

all seq have one address field, by default address field is declared as rand, from testcase I am giving input to the address field,
but when I execute that rand seq valid,input from testcase is not passed, I am getting random value.my question is,there is any way to replace address field with my testcase input value instead of random seq.

2

In reply to RAMANATHAN:

hi Ramanathan,
am observed your question,write the other sequence without rand variable and pass it to dut.

i hope it is useful to you!!!

see the example below:
Class seq_lib extends uvm_sequence_library #(transaction_class);
uvm_object_utils(seq_lib) uvm_sequence_library_utils(seq_lib)
function new(string name = “”);
super.new(name);
init_sequence_library();
endfunction
endclass
seq_lib lib = seq_lib::type_id::create();
lib.add_sequence( seq1::get_type() );
lib.add_sequence( seq2::get_type() );
lib.selection_mode = UVM_SEQ_LIB_RAND;
if ( !lib.randomize())
lib.start(m_env.m_seqr);

3

The issue is that you are using the UVM mechanism to create and randomize a random sequence for you. By doing this, you lose all ability to control the randomization.

Instead, you should select a random sequence as part of your test which will then give you the ability to control your address field.