How we can check functionality of RTL by functional coverage?

SystemVerilog
1

module dff(output q,q_bar,input clk,d,reset);
always @(posedge clk or negedge reset) begin
q<=d;
q_bar<=~d;
end
endmodule

 In above D flipflop module i don't  write any functionality of reset.Then how can I check that my functionality of reset is covered or not using functional  coverage?
2

How we can check functionality of RTL by functional coverage?

Functionality of a design and coverage are two different things:
Functionality of design (e.g., RTL) means checking that the design meets the requirements. However,

coverage: The percentage of verification objectives that have been met. It is used as a metric for evaluating the progress of a verification project in order to reduce the number of simulation cycles spent in verifying a design. A measure of the occurrence of certain behavior during (typically dynamic) verification and, therefore, a measure of the completeness of the (dynamic) verification process. (Also see functional coverage and test coverage). In formal verification, if a cover of a property passes, then the formal verification tool reports a trace. If it fails, it means that the described property cannot be reached (see 7.4.5 and below for more discussion).
functional coverage: A user-defined metric that measures how much of the design specification, as enumerated by features in the test plan, has been exercised. It can be used to measure whether interesting scenarios, corner cases, specification invariants, or other applicable design conditions have been observed, validated and tested.

For your example, you can use assertions to verify the design (e.g., assert property) and coverage of sequences (e.g., cover sequence) to verify occurrences of test sequences.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

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