Hi All,
My requirement is to toggle a signal named X from 0 to 1 and 1 to 0.
And to do that i need to configure a register R to 1 to make X 0 to 1 and R to 2 (any value apart from 1) to make X 1 to 0.
below is what i have tried but not sure if i’m following proper sysntax
example1 :
assert_R_X : assert property
(@(posedge clk) disable iff (rst)
((state) && (rdy) && (R==1) |=> (X==1))
else if (state) && (rdy) && (R==2) |=> (X==0));
example2 :
sequence r_1_x_1;
((state) && (rdy) && (R==1));
endsequence
sequence r_2_x_0;
((state) && (rdy) && (R==2));
endsequence
assert_R_X : assert property
(@(posedge clk) disable iff (rst)
if (r_1_x_1) |=> (X==1);
else if (r_2_x_0) |=> (X==1));