How to write Assertions for timing registers

SystemVerilog
21

Hi,
I want to implement implement below piece of code in form of assertions;

if(a==0)
{
for(i=0;i<=b; i++)
{
if(a==0) printf(“condition is satisfied”);
else printf(“condition is failed”);
}
}
i want to check if the signal remains in same position till the count value, how do i achive this through assertion please help.

22 
module test_case2;
	logic a=1'b1, clk=1'b0;
	bit[0:2] b;
//    if(a==0)
//{
//for(i=0;i<=b; i++)
//{
//if(a==0) printf("condition is satisfied");
//else printf("condition is failed");
//}
//}
//i want to check if the signal remains in same position till the count value, 
// how do i achive this through assertion please help.
	default clocking cb_ck1 @ (posedge(clk));  endclocking 
	property p_stable4n_0;
		int v_b; 
		($fell(a), v_b=b) |=> 
                   ($stable(a), v_b=v_b-1)[*0:$] ##1 v_b==0 && $stable(a);   
	endproperty : p_stable4n_0

	property p_stable4n;
		int v_b; 
		($fell(a), v_b=b) |=> (a==1'b0, v_b=v_b-1)[*0:$] ##1 v_b==0 && a==1'b0;   
	endproperty :p_stable4n
	ap_stable4n_0:  assert property(p_stable4n_0);

	ap_stable4n: assert property(p_stable4n);
	initial forever #10 clk=!clk;  
	always_ff @ (posedge(clk)) begin
		if(!randomize(a, b))  $error("randomization failure"); 
	end

endmodule :test_case2

See simulation results at http://SystemVerilog.us/test_case2.JPG
(code is also at http://SystemVerilog.us/test_case2.sv )

Ben Cohen, Design and verification expert (310) 997-2187
http://www.systemverilog.us/ ben@systemverilog.us

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