How to write Assertions for timing registers

SystemVerilog
4

In reply to ben@SystemVerilog.us:

Hi Ben,

Thanks for replying to the query,
property a4;
logic [15:0] v_Tnvh_count;
@(posedge clk)(fell(FLASH.erase), v_Tnvh_count=0) |=> (1, v_Tnvh_count=v_Tnvh_count+1'b1)[*1:] ##1 (v_Tnvh_count == Tnvh_count) ##[1:$] ($fell(FLASH.nvstr));
endproperty : a4
Assertion4: assert property (a4);

problem here is this assertions is getting activated at every posedge of clk and waiting for $fell(FLASH.erase) event, but this event occurs only once, assertion finishes and gets activated again in the next clk cycle, hence assertion is failing. how do i avoid un necessary failing of assertion