How to write Assertions for timing registers

SystemVerilog
2

This should work:

module clk_period;
	logic [3:0] thv_count;
	int clk_period=10;
	bit clk; 
	default clocking cb_ck1 @ (posedge(clk));  endclocking   
	initial forever #10 clk=!clk; 
	assign thv_count = (23*clk_period);
//  assert property(@(posedge clk)) ($rose(FLASH.prog) && ($rose(FLASH.erase)) |->
//     ##[thv_count : $] ($rose(FLASH.nvstr));
	property p_flash;
		logic [3:0] v_thv_count;
		($rose(FLASH.prog) && ($rose(FLASH.erase)), v_thv_count=0) |=> 
		(1, v_thv_count=v_thv_count+1'b1)[*1:$] ##1 v_thv_count==thv_count // get to thv_count
		##[0:$] ($rose(FLASH.nvstr)); // changed from ##[1:$] 

endmodule

Ben Cohen, Design and verification expert (310) 997-2187
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook, 3rd Edition, 2013 ISBN 0-9705394-3-6
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example, 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115