How to write assertions for a Clock divider

SystemVerilog
9

In reply to ben@SystemVerilog.us:

Yes agreed , that first match is not needed here.
I also tried your solution but it gives me compile error : -
// But the above is same as

property even_rose_div(clk_div , n) ;
let MY_DELAY = VALUE[2*n+:2] ; // VALUE is a constant
$rose(div_clk[n]) |=> ##MY_DELAY $fell(div_clk[n]);

Here value is coming from parameter ,where n is an argument. But it is giving me compile error.
*E :- Expected specification terminator “;”.

I think the local variable is the best way to check divider.