In reply to ben@SystemVerilog.us:
Thanks Ben for the suggestion.
I tried your sample testbench on edaplayground. Few changes I have to make inside sequence I was not able to assign value.
line 3 int v=count; Also I tried moving the sequence inside the module and it worked fine. There was no need for a package.
Below is the link for the same.
The requirement is ambiguous and yes there will be a fixed pattern but that pattern can change in future, so from your code, I wanted to know how are we making sure the 5 times a is high out of 6 clk cycles as see we are using [*1:$] which makes it check till the end.