In reply to advaneharshal:
- Your requirements are ambiguous. When you say ““a” should be high for 5 out of 6 sys_clk cycles. The 5 cycles can be of any pattern”, what do you mean by 5 cycles can be of any pattern. If they are not contiguous, meaning you can have any 5 non-contiguous ONEs within any 6 cycles, then there is a need for a frame signal for those 6 cycles.
- Commenting on your code, $rose(clk)[*6] is always false, as the rose of a signal cannot be repeated more than once, by definition of the rose; it has to be a ZERO in the previous cycle.
- Wrote some code for the repeat.
- see my papers links in my signature.
// the sig a should be high for 5 out of 6 sys_clk cycles.
// The 5 cycles can be of any pattern.
// this link offers an interesting approach to handle dynamic repeats
// and delays for sequences.
// http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf
package sva_delay_repeat_pkg;
sequence dynamic_repeat(q_s, count);
int v=count;
(1, v=count) ##0 first_match((q_s, v=v-1'b1) [*1:$] ##0 v<=0);
endsequence
sequence dynamic_delay(count);
int v;
(1, v=count) ##0 first_match((1, v=v-1'b1) [*0:$] ##1 v<=0);
endsequence
endpackage
import uvm_pkg::*; `include "uvm_macros.svh"
import sva_delay_repeat_pkg::*;
module top;
timeunit 1ns; timeprecision 100ps;
bit clk, a, b;
int rpt=5;
default clocking @(posedge clk); endclocking
initial forever #10 clk=!clk;
// a==1 for 5 consecutive cycles
ap_4out_of5: assert property(@ (posedge clk)
$rose(a) |-> a[*5] ##1 $fell(a) );
// a==1 for rpt consecutive cycles
ap_4out_of5_rpt: assert property(@ (posedge clk)
$rose(a) |-> dynamic_repeat(a, rpt) ##1 $fell(a) );
initial begin
bit va, vb;
repeat(200) begin
@(posedge clk);
if (!randomize(va, vb) with
{ va dist {1'b1:=5, 1'b0:=1};
vb dist {1'b1:=1, 1'b0:=2};
}) `uvm_error("MYERR", "This is a randomize error")
a <= va;
b <= vb;
end
$stop;
end
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- VF Horizons:PAPER: SVA Alternative for Complex Assertions | Verification Academy
- http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf
- “Using SVA for scoreboarding and TB designs”
http://systemverilog.us/papers/sva4scoreboarding.pdf - “Assertions Instead of FSMs/logic for Scoreboarding and Verification”
October 2013 | Volume 9, Issue 3 | Verification Academy - SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy