I have a working SystemC code as shown below which I am trying to convert into Systemverilog to learn it. although original code was very large but I shortened it down to narrow issues
typedef int token_type;
struct packet
{
int src_x, src_y;
int dest_x, dest_y;
token_type token;
packet(int sx = -1, int sy = -1, int dx = -1, int dy = -1,
token_type t = token_type())
: src_x(sx), src_y(sy), dest_x(dx), dest_y(dy), token(t)
{
}
bool operator==(const packet &x) const
{
return (x.src_x == src_x) && (x.src_y == src_y)
&& (x.dest_x == dest_x) && (x.dest_y == dest_y)
&& (x.token == token);
}
}; // struct packet
std::ostream &operator<<(std::ostream &o, const packet &p);
void sc_trace(sc_trace_file *tf, const packet &p, const std::string &name);
SC_MODULE(router)
{
sc_in<bool> clock; // port for the global clock
enum { PE = 0, PORTS };
sc_in<packet> port_in[PORTS]; // input ports
sc_out<packet> port_out[PORTS]; // output ports
void main();
SC_CTOR(router)
: x_(-1), y_(-1)
{
SC_METHOD(main);
sensitive << clock.pos();
}
void set_xy(int x, int y);
protected:
std::list<packet> out_queue_[PORTS]; // output queues
int x_, y_; // location of the router
}; // router
I am calling above functions as shown below
std::ostream &operator<<(std::ostream &o, const packet &p)
{
char buf[100];
return o << buf << ", " << p.token;
}
void sc_trace(sc_trace_file *tf, const packet &p, const std::string &name)
{
}
void router::main()
{
assert((x_ != -1) && (y_ != -1));
}
void router::set_xy(int x, int y)
{
assert((x_ == -1) && (y_ == -1));
assert((x != -1) && (y != -1));
x_ = x;
y_ = y;
}
and my main program runs all of above with below code
SC_MODULE(top)
{
public:
enum { N = 1 }; //enum { N = 2 };
router *routers[N];
sc_signal<packet> router_to_pe[N], pe_to_router[N];
sc_signal<bool> clock;
SC_CTOR(top)
{
create_network();
}
protected:
void create_network()
{
for (int i = 0; i < N; ++i)
{
char name[100];
sprintf(name, "router%d", i);
// create router
routers[i] = new router(name);
routers[i]->set_xy(i, 0);
routers[i]->clock(clock);
routers[i]->port_out[router::PE](router_to_pe[i]);
routers[i]->port_in[router::PE](pe_to_router[i]);
}
}
}; // top
int sc_main(int argc, char *argv[])
{
srand(0);
top top_module("top");
printf("cycle 0 ================================\n");
sc_start(0, SC_NS);
for (int i = 1; i < 20; i++) {
printf("cycle %2d ================================\n", i);
top_module.clock.write(1);
sc_start(10, SC_NS);
top_module.clock.write(0);
sc_start(10, SC_NS);
}
cin.get();
return 0;
}
Systemverilog code I have written to date is shown below and errors I see are shown on lines which occur on compilation
typedef int token_type;
class pkt;
int src_x, src_y;
int dest_x, dest_y;
token_type token;
function new(int sx = -1, int sy = -1, int dx = -1, int dy = -1,
token_type t);
this.src_x=sx; this.src_y=sy;
this.dest_x=dx; this.dest_y=dy;
this.token=t;
endfunction
function logic operator(pkt x);
return (x.src_x == src_x) && (x.src_y == src_y)
&& (x.dest_x == dest_x) && (x.dest_y == dest_y)
&& (x.token == token);
endfunction
endclass
pkt packet;
//parameter PE = 4'b0000,
//PORTS = 4'b0101;
module router(clock,port_in,port_out);
input clock;
enum { PE = 0, PORTS } ports;
packet out_queue_[$:PORTS];//error here is syntax: error unexpected '$'
input [0:packet] port_in[0:PORTS];//error here is illegal reference to class "packet"
output [0:packet] port_out[0:PORTS];
int x_, y_;
always @(posedge clock)
begin
assert((x_ != -1) && (y_ != -1));
end
endmodule
I wanted to know how to implement list of type packet and arrays of sc_in and sc_out of type packet in Systemverilog, or my total approach needs to change?