How to verify the correct functionality of the ready output signal from DUT in ready/valid interface?

SystemVerilog
4

In reply to Michael54:

Your last sentence makes me think there is still a lot more to your problem than you have revealed. What do buffers and flops have to do with interface signals? And when you “interface” you mean these are ports of the dut? And when does the ready signal first get asserted?

Would this work?

 initial fork
    @(posedge clk iff ready) 
    forever @(posedge clk)
      if  ( !ready && vcounter <  64 ) $error("ready deasserted before 64 valid transactions",, vcounter);
    else if (ready && vcounter >= 64 ) $error("ready not deasserted after 64 valid transactions",, vcounter);
    forever @(posedge clk iff ready && valid) vcounter <= vcounter + 1;
  join_any