How to verify the correct functionality of the ready output signal from DUT in ready/valid interface?

SystemVerilog
3

In reply to dave_59:

  1. Looking to do it without using an assertion.
  2. “Valid transaction” defined when both ready and valid signals of the interface are set to ‘1’.
  3. There might be cases when the ready signal is high ‘1’, but valid signal is ‘0’.
  4. From beginning of test, ideally would be great if this checker could be breathing and active during the whole test.
  5. The ready signal should be de-asserted after the 64th valid transaction.

Honestly, there might be many buffers and flops in the DUT (from experience of verifying other designs), so I wonder how this checker could be tight and correct.