So we have to build reference model to verify DUT. But how do we know the correctness of reference model? Also, what’s the point if designer build reference model himself? It’s just him rewriting DUT in systemverilog language. Does UVM platform have to be built by a different team/person who know nothing but spec to make the verification valid?
In reply to patrick1258:
You are asking a very important but common question of modelling. Each model you are creating might be not correct and needs to be verified. In the UVM we are trying to use different kinds of ref models, i.e either a transaction-based model or a C/C++ model. These kins of models have differnt errors as the DUT commonly has. C/C++ models are coming out of system modelling in C/C++. These kind of models will be verified against a specifictaion desription in C/C++.
TL-models are considering transaction based processing. This is completely differnt to a cycle-based description (as the DUT is).
In any way if you are facing an error in the scoreboard you have to chec if it comes out of the DUT or the ref model.