In reply to dddvlsique:
I believe you do not want to verify this scenario. Instead you want to find out what is wrong, i.e. debugging this scenario.
There are different approaches.
You have to find out if this is a problem of your testbench (RAL model) or does it happen in the design. The reson might be you have a wrong access mode or bits have been swapped and there will be more.
To give you a good advice depends on mor information as you gave so far.