Hi,
2x1 glitch free mux having two input clocks (I0, I1), both clocks are asynchronous to each other. Th select line is asynchronous to inputs I0, I1. The output of mux is glitch free clock (The select signal is toggling at different time). How to verify whether the output clock has really glitch free or not using automation.
I want to verify this by using System verilog constructs.
Tell me the way without using Clock Domain Crossing (CDC) tool.