How to verify FSM for Pattern detection

SystemVerilog
,
1

Hello,

How do I verify the Pattern Detector FSM DUT.
Pattern is 10110110. Is it possible to constrain the stimulus such
that the pattern 10110110 occurs often with other combinations.

Is just declaring randc bit[7:0] , randomize and sending patterns
serially back to back is sufficient?

Thanks
JeffD

2

In reply to dvuvmsv:

I think you meant more often. You can use a dist constraint:

class A;
 rand bit [7:0] pattern;
 rand bit mode;
 constraint c{
     mode dist {1:=66, 0:=33};
     mode -> pattern == 8'b10110110;
   }
endclass
3

Hi Dave,
Thanks for the quick response.
I meant the pattern 10110110 will give pattern_detected = 1;
If I randomize rand bit [7:0] without constraints, I may never
get a pattern like 10110110 or it rarely occurs.

In your solution mode dist {1:66, 0:33} means 1 occurs 66% and 0 occurs 33%

What does mode → pattern == 8’b10110110 mean ?

Thanks
JeffD

4

In reply to dvuvmsv:

Hi JeffD,

It mean that assume for every 10 randomization calls we get mode==1 for at least 6 and maximum of 7 times. So overall, when the mode==1,you get the right pattern. 3/4 out of 10 you get the mode==0 and thus pattern has different value.

Thanks,
Mahesh.

5

Thank you all