How to use "uvm_hdl_force"?

UVM
,
1

Hi,

I am trying to use uvm_hdl_force feature to force one of the internal design signal.
I have wrote the code as following.

The code exists inside the driver.
uvm_hdl_force(“test.top.design1.VALUE_REG”,1’b1);

However, I am getting the following ERROR message.
“ERROR: VPI VISNOW”
Attempting to place a value into “test.top.design1.VALUE_REG” which does not have write access.

Please let me know what is the correct way to use uvm_hdl_force.

Thanks.
Karan

2

This is a tool specific problem when using the VPI. Read your tool’s user manual.

3

Needed to add -access +rw

Thanks.
Karan